@inproceedings{6ec923f4f9064fb48a0a61aaa80fbac2,
title = "High-speed interfaces for analog, iterative VLSI decoders",
abstract = "The design of various high-speed interface architectures for off-chip connections to and from analog, iterative VLSI decoders is discussed. It is shown that for applications with high transmission rates and low to medium accuracy, MOSFET-only R-2R ladders in combination with switched-current memory cells are ideally suited, due to their current mode nature as well as their power and area efficiency. It is expected that data rates well above 100MS/s can be obtained.",
author = "Markus Helfenstein and Felix Lustenberger and Andrea Loeliger and Felix Tarkoy and Moschytz, {George S.}",
year = "1999",
language = "אנגלית",
isbn = "0780354729",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "II--428 -- II--431",
booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",
note = "Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 ; Conference date: 30-05-1999 Through 02-06-1999",
}