High speed dual mode logic carry look ahead adder

I Levi; O Bass; A Kaizerman; A Belenky; A Fish

High speed dual mode logic carry look ahead adder

I Levi, O Bass, A Kaizerman, A Belenky, A Fish

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

Original language	American English
Title of host publication	2012 IEEE International Symposium on Circuits and Systems
Publisher	IEEE
State	Published - 2012

Bibliographical note

Place of conference:Seoul

Cite this

@inproceedings{e2a3be2d7b054a86829f0cb6658c6d5d,

title = "High speed dual mode logic carry look ahead adder",

abstract = "A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.",

author = "I Levi and O Bass and A Kaizerman and A Belenky and A Fish",

note = "Place of conference:Seoul",

year = "2012",

language = "American English",

booktitle = "2012 IEEE International Symposium on Circuits and Systems",

publisher = "IEEE",

}

TY - GEN

T1 - High speed dual mode logic carry look ahead adder

AU - Levi, I

AU - Bass, O

AU - Kaizerman, A

AU - Belenky, A

AU - Fish, A

N1 - Place of conference:Seoul

PY - 2012

Y1 - 2012

N2 - A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

AB - A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

UR - https://scholar.google.co.il/scholar?q=High+Speed++Dual+Mode+Logic+Carry+Look+Ahead+Adder+&btnG=&hl=en&as_sdt=0%2C5

M3 - Conference contribution

BT - 2012 IEEE International Symposium on Circuits and Systems

PB - IEEE

ER -

High speed dual mode logic carry look ahead adder

Abstract

Bibliographical note

Other files and links

Fingerprint

Cite this