High speed Dual Mode Logic Carry Look Ahead Adder

Itamar Levi, Ori Bass, Asaf Kaizerman, Alexander Belenky, Alexander Fish

Research output: Contribution to conferencePaperpeer-review

35 Scopus citations

Abstract

A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

Original languageEnglish
Pages3037-3040
Number of pages4
DOIs
StatePublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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