High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar; Luis Miguel Procel; Lionel Trojman; Marco Lanuzza; Ramiro Taco

doi:10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Ricardo Escobar, Luis Miguel Procel, Lionel Trojman, Marco Lanuzza, Ramiro Taco

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.

Original language	English
Title of host publication	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728176703
DOIs	https://doi.org/10.1109/LASCAS51355.2021.9459151
State	Published - 21 Feb 2021
Externally published	Yes
Event	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021 - Arequipa, Peru Duration: 22 Feb 2021 → 25 Feb 2021

Publication series

Name	2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021

Conference

Conference	12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021
Country/Territory	Peru
City	Arequipa
Period	22/02/21 → 25/02/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

Keywords

CMOS
Dual-mode logic
arithmetic circuits
binary comparator

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/LASCAS51355.2021.9459151

Cite this

Escobar, R., Procel, L. M., Trojman, L., Lanuzza, M., & Taco, R. (2021). High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. In 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021 Article 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS51355.2021.9459151

Escobar, Ricardo ; Procel, Luis Miguel ; Trojman, Lionel et al. / High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

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abstract = "This paper presents an energy-efficient single-clock-cycle binary Dual-Mode Logic (DML)-based comparator optimized to operate in the dynamic mode. The parallel-prefix architecture is implemented to ensure high speed, whereas low power consumption is guaranteed by reducing the switching activities of internal nodes. Domino Logic (DL) and DML implementations are compared in terms of delay and energy for different supply voltages in the 32 nm technology. We demonstrate an average improvement of 5% in both energy and delay when the DML design is operating in the dynamic mode compared to its conventional domino counterpart. Moreover, the DML design operating in the static mode allows to save up to 43% energy consumption compared to the equivalent domino logic-based implementation.",

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Escobar, R, Procel, LM, Trojman, L, Lanuzza, M & Taco, R 2021, High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. in 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021., 9459151, 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021, Institute of Electrical and Electronics Engineers Inc., 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021, Arequipa, Peru, 22/02/21. https://doi.org/10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. / Escobar, Ricardo; Procel, Luis Miguel; Trojman, Lionel et al.
2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9459151 (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Escobar R, Procel LM, Trojman L, Lanuzza M, Taco R. High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. In 2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9459151. (2021 IEEE 12th Latin American Symposium on Circuits and Systems, LASCAS 2021). doi: 10.1109/LASCAS51355.2021.9459151

High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator

Abstract

Publication series

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Bibliographical note

Keywords

UN SDGs

Access to Document

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