High Density GC-eDRAM Design in 16nm FinFET

Amir Shalom; Robert Giterman; Adam Teman

doi:10.1109/ICECS.2018.8618019

High Density GC-eDRAM Design in 16nm FinFET

Amir Shalom, Robert Giterman, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Gain-cell embedded DRAM (GC-eDRAM) is an interesting alternative to conventional six-transistor (6T) static random access memory (SRAM) cells, offering higher density, lower leakage, and two-ported operation. However, process scaling and the migration to FinFET technologies have brought new challenges to the design of GC-eDRAM cells, including significant changes in device leakage characteristics, resulting in reduced data retention times (DRTs) and new layout rules, affecting the area benefits of known GC-eDRAM topologies. In this paper, for the first time, we examine different GC-eDRAM topologies in a foundry-based 16 nm FinFET technology. Based on this analysis, we develop a methodology for the best practice design of GC-eDRAM in FinFET technologies, based on the transistor characteristics and layout constraints. The developed methodology demonstrates the potential benefits of GC-eDRAM in 16 nm FinFET technology and beyond.

Original language	English
Title of host publication	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	585-588
Number of pages	4
ISBN (Electronic)	9781538695623
DOIs	https://doi.org/10.1109/ICECS.2018.8618019
State	Published - 2 Jul 2018
Event	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Duration: 9 Dec 2018 → 12 Dec 2018

Publication series

Name	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Conference

Conference	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Country/Territory	France
City	Bordeaux
Period	9/12/18 → 12/12/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Access to Document

10.1109/ICECS.2018.8618019

Cite this

Shalom, A., Giterman, R., & Teman, A. (2018). High Density GC-eDRAM Design in 16nm FinFET. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 (pp. 585-588). Article 8618019 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2018.8618019

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Shalom, A, Giterman, R & Teman, A 2018, High Density GC-eDRAM Design in 16nm FinFET. in 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018., 8618019, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 585-588, 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8618019

High Density GC-eDRAM Design in 16nm FinFET. / Shalom, Amir; Giterman, Robert; Teman, Adam.
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 585-588 8618019 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Shalom A, Giterman R, Teman A. High Density GC-eDRAM Design in 16nm FinFET. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 585-588. 8618019. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). doi: 10.1109/ICECS.2018.8618019

High Density GC-eDRAM Design in 16nm FinFET

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