Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Raj Kumar; Arvind Kumar

doi:10.1007/s12633-020-00705-w

Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Raj Kumar, Arvind Kumar

Panjab University

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO₂ and Hf_xTi_1-xO₂) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO₂ on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10⁻¹⁴ to 10⁻¹⁷ and I_ON/I_OFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and I_ON/I_OFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

Original language	English
Pages (from-to)	2177-2184
Number of pages	8
Journal	Silicon
Volume	13
Issue number	7
DOIs	https://doi.org/10.1007/s12633-020-00705-w
State	Published - Jul 2021
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2020, Springer Nature B.V.

Keywords

DIBL
Hetro-dielectric (HD)
Junctionless
Leakage current
Nanotube (NT)
SS

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10.1007/s12633-020-00705-w

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title = "Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)",

abstract = "This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1-xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.",

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AB - This paper proposed Hetero-Dielectric (HD) Oxide-Engineered Junctionless double gate all around nanotube (DGAA-NT) FET for performance enhancement in low power circuits. In HD configuration, hafnium based high-k dielectric (HfO2 and HfxTi1-xO2) as gate oxide (for inner as well as outer gate oxide) is introduced on source side and SiO2 on drain side of HD JL-DGAA-NT FET. The tunnelling width and source-to-channel barrier height are significantly increased in the HD-JL-DGAA-NT FET as compared JL-DGAA-NT FET, causes the reduction in leakage current an order of 10−14 to 10−17 and ION/IOFF ratio increased by 54%. It has been observed that side spacer with suitable dielectric constant can be considered to improve the performance of device. Further, Subthreshold slope (SS) and DIBL and ION/IOFF current ratio has shown tremendous improvement on reducing channel thickness from 10 nm to 8 nm. It has been found that in HD-JL-DGAA-NT FET provides 25% and 57% improvement in SS and DIBL respectively. Therefore, HD-JL-DGAA-NT FET with adequate design parameters and dielectric material may be used for future digital applications.

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Hetro-Dielectric (HD) Oxide-Engineered Junctionless Double Gate all around (DGAA) Nanotube Field Effect Transistor (FET)

Abstract

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Keywords

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