HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems

Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

TThe RISC-V architecture has recently emerged as a popular open source option for the design of general purpose cores with a wide spectrum of operating specifications. In this paper, we present HAMSA-DI, a small footprint, energy-efficient, embedded RISC-V core, featuring a dynamically scheduled, inorder, dual-issue processing pipeline, supporting the popular Xpulp extensions. The proposed cost-effective dual-issue implementation provides a significant performance boost and improved energy-efficiency over baseline low-power cores under common benchmarks. These include a CoreMark score of 3.48 CM/MHz (+22%) and an Embench score of 1.3 (+13%) with certain benchmarks displaying as much as 22% less energy than the baseline CV32E40P core. The proposed design was fabricated as part of a 16 nm test chip, running at 1 GHz with an 0.8V supply voltage. Silicon measurements demonstrate that the proposed core can improve performance by as much as 8 × for programs operating with full dual-issue utilization with energy-efficiency improving by as much as 6.5

Original languageEnglish
Pages (from-to)223-236
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume71
Issue number1
DOIs
StatePublished - 1 Jan 2024

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • RISC-V
  • dual-issue
  • embedded processor
  • energy-efficient
  • low-power
  • small-footprint

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