Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

Raj Kumar; Arvind Kumar

doi:10.1007/s00339-020-04217-7

Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

Raj Kumar, Arvind Kumar

Panjab University

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO₂ and Hf_xTi_1−xO₂) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10^–16) and improvement in I_ON/I_OFF ratio (~ 10¹¹) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the I_ON/I_OFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.

Original language	English
Article number	26
Journal	Applied Physics A: Materials Science and Processing
Volume	127
Issue number	1
DOIs	https://doi.org/10.1007/s00339-020-04217-7
State	Published - Jan 2021
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH, DE part of Springer Nature.

Keywords

Dielectric constant
GME
Gate stacked (GS)
I/I ratio
Si-nanotube

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title = "Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications",

abstract = "In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO2 and HfxTi1−xO2) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10–16) and improvement in ION/IOFF ratio (~ 1011) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the ION/IOFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.",

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note = "Publisher Copyright: {\textcopyright} 2021, The Author(s), under exclusive licence to Springer-Verlag GmbH, DE part of Springer Nature.",

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doi = "10.1007/s00339-020-04217-7",

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N2 - In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO2 and HfxTi1−xO2) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10–16) and improvement in ION/IOFF ratio (~ 1011) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the ION/IOFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.

AB - In this paper, gate-stacked gate-material-engineered junctionless nanotube MOSFET (GS GME JL NTMOSFET) was proposed for digital circuits. In GS configuration, hafnium-based high-k dielectrics (HfO2 and HfxTi1−xO2) were used in gate-stacked engineering (for inner as well as outer gate oxide). The performance of proposed device was compared with non-stacked GME JL NTMOSFET and analysed. GS GME JL NTMOSFET offered a significant reduction in leakage current (~ 10–16) and improvement in ION/IOFF ratio (~ 1011) as compared to non-stacked device. It was found that side spacer with suitable dielectric constant can be considered to improve the ION/IOFF ratio, SS, DIBL of the proposed device. Furthermore, the CMOS inverter circuit of purposed device was designed to investigate its digital performance. Therefore, GS GME JL NTMOSFET with adequate design parameters and dielectric material may be used in future digital applications.

KW - Dielectric constant

KW - GME

KW - Gate stacked (GS)

KW - I/I ratio

KW - Si-nanotube

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Hafnium based high-k dielectric gate-stacked (GS) gate material engineered (GME) junctionless nanotube MOSFET for digital applications

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Keywords

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