GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. This problem is aggravated due to the impact of process-voltage-temperature (PVT) variations at deeply scaled technology nodes and low voltages. In this brief, we present a gain-cell embedded DRAM (GC-eDRAM) with body-bias compensated readout, which is dynamically configured to extend the data retention time (DRT) of the memory under varying operating conditions. The proposed GC-eDRAM exploits the body-biasing capabilities of FD-SOI technology to adjust the switching threshold of the sense inverter under PVT variations. An additional, unbiased, sense inverter is added to provide a dual-sampling mechanism to the readout path, enabling error detection to further reduce design guard bands. An 8-kb GC-eDRAM with integrated body-bias compensated readout and error detection was implemented in 28-nm FD-SOI technology. Silicon measurements of the manufactured array demonstrate up to 75% DRT improvement and up to 86% energy savings under PVT and frequency variations compared to a conventional guard banded memory design.