Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis

Shashi Bala; Raj Kumar; P. N. Hrisheekesha; Harpal Singh; Arvind Kumar

doi:10.1007/s12633-022-02071-1

Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis

Shashi Bala, Raj Kumar, P. N. Hrisheekesha, Harpal Singh, Arvind Kumar

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO₂ which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10⁻¹⁶) and high I_ON/I_OFF ratio (~10¹¹) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as I_ON/I_OFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications.

Original language	English
Pages (from-to)	1037-1047
Number of pages	11
Journal	Silicon
Volume	15
Issue number	2
DOIs	https://doi.org/10.1007/s12633-022-02071-1
State	Published - Jan 2023
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 2022, The Author(s), under exclusive licence to Springer Nature B.V.

Funding

Raj Kumar acknowledges the UGC, India for the financial assistance and UIET (ECE), Panjab University for providing Lab facility.

Funders	Funder number
UIET
University Grants Commission
Panjab University

Keywords

Gate stack (GS)
Junctionless
Leakage current
Nanotube (NT)

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10.1007/s12633-022-02071-1

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abstract = "This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO2 which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10−16) and high ION/IOFF ratio (~1011) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as ION/IOFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications.",

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KW - Gate stack (GS)

KW - Junctionless

KW - Leakage current

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Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis

Abstract

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Keywords

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