TY - GEN
T1 - Gate diffusion input (GDI) logic in standard CMOS nanoscale process
AU - Morgenshtein, Arkadiy
AU - Shwartz, Idan
AU - Fish, A.
N1 - Place of conference:Israel
PY - 2010
Y1 - 2010
N2 - In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.
AB - In this paper CMOS compatible Gate Diffusion Input (GDI) design technique is proposed. The GDI method enables the implementation of a wide range of complex logic functions using only two transistors. This method is suitable for the design of low-power logic gates, with a much smaller area than Static CMOS and existing PTL techniques. As opposite to our originally proposed GDI logic, the modified GDI logic is fully compatible for implementation in a standard CMOS process. Simulations of basic GDI gates under process and temperature corners in 40nm CMOS process are shown and compared to similar CMOS gates. We show that while having the same delay, GDI gates achieve leakage and active power reduction of up to 70% and 50%, respectively.
UR - https://scholar.google.co.il/scholar?q=Gate+Diffusion+Input+%28GDI%29+Logic+in+Standard+CMOS+Nanoscale+Process+&btnG=&hl=en&as_sdt=0%2C5
M3 - Conference contribution
BT - Electrical and Electronics Engineers in Israel (IEEEI), 2010 IEEE 26th Convention of
PB - IEEE
ER -