TY - JOUR
T1 - Gate-diffusion input (GDI)
T2 - A power-efficient method for digital combinatorial circuits
AU - Morgenshtein, Arkadiy
AU - Fish, Alexander
AU - Wagner, Israel A.
PY - 2002/10
Y1 - 2002/10
N2 - Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.
AB - Gate diffusion input (GDI) - a new technique of low-power digital combinatorial circuit design - is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are reported, and measurements of a test chip are presented.
KW - Analysis
KW - CMOS
KW - Delay
KW - Digital
KW - Low-power design
KW - Performance
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=0036819196&partnerID=8YFLogxK
U2 - 10.1109/tvlsi.2002.801578
DO - 10.1109/tvlsi.2002.801578
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AN - SCOPUS:0036819196
SN - 1063-8210
VL - 10
SP - 566
EP - 581
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 5
ER -