Gain-Cell Embedded DRAM under Cryogenic Operation-A First Study

Esteban Garzon, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman

Research output: Contribution to journalArticlepeer-review

19 Scopus citations

Abstract

Operating circuits under cryogenic conditions is effective for a large spectrum of applications. However, the refrigeration requirement for the cooling of cryogenic systems introduces serious issues in terms of power dissipation. Gain-cell embedded dynamic random access memory (GC-eDRAM) is a low-area, logic-compatible embedded memory alternative to static random access memory (SRAM), which has the potential to provide ultralow-power operation under cryogenic conditions due to the lower leakages at these temperatures. In this article, we present the first comparative design exploration of GC-eDRAM under cryogenic conditions performed with transistor models characterized based on actual silicon measurements under temperatures as low as 77 K. Our study shows that the two-transistor (2T)-based GC-eDRAM configurations turn out to be the best solutions for very lowerature operation. In particular, the 2T mixed GC-eDRAM configurations allow read sensing margin improvements (up to 99%) within the 2T-based configurations while at the same time excel in terms of data retention time (+44%) and power consumption (-27%) when compared to more complex GC-eDRAM topologies. Moreover, even better improvements in terms of area (-73%), leakage power (-97%), retention power (-76%), and energy (-66%) are observed when compared to conventional 6T-SRAM.

Original languageEnglish
Article number9442391
Pages (from-to)1319-1324
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume29
Issue number7
DOIs
StatePublished - Jul 2021

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

Keywords

  • Cryogenic
  • data retention time (DRT)
  • edge-direct tunneling
  • embedded memory
  • gain-cell embedded DRAM (GC-eDRAM)
  • subthreshold leakage

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