TY - CHAP
T1 - From Verification to Synthesis
AU - Peled, D.
PY - 2015
Y1 - 2015
N2 - Model checking methods are used to verify the correctness of digital circuits and
code against their formal specification. In case of design or programming errors, they
provide counterexample evidence of erroneous behavior. Model checking techniques suffer
from inherent high complexity. New model checking methods attempt to speed it up and
reduce the memory requirement. Recently, the more ambitious task of converting the formal
specification automatically into correct-by-design code has gained significant progress. In this paper, automata-based techniques for model checking and automatic synthesis are described.
AB - Model checking methods are used to verify the correctness of digital circuits and
code against their formal specification. In case of design or programming errors, they
provide counterexample evidence of erroneous behavior. Model checking techniques suffer
from inherent high complexity. New model checking methods attempt to speed it up and
reduce the memory requirement. Recently, the more ambitious task of converting the formal
specification automatically into correct-by-design code has gained significant progress. In this paper, automata-based techniques for model checking and automatic synthesis are described.
UR - https://books.google.co.il/books?hl=en&lr=&id=rykxCgAAQBAJ&oi=fnd&pg=PA204&dq=info:AC0KC0R-0F8J:scholar.google.com&ots=PGDLsIrBac&sig=lJoKJPi_q-YAF8OgY_xCH14SK0U&redir_esc=y#v=onepage&q&f=false
U2 - 10.3233/978-1-61499-495-4-204
DO - 10.3233/978-1-61499-495-4-204
M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.chapter???
SN - 978-1-61499-494-7
T3 - NATO Science for Peace and Security Series - D: Information and Communication Security
SP - 204
EP - 307
BT - Dependable Software Systems Engineering
A2 - Pretschner, A.
A2 - Peled, D.
A2 - Irlbeck, M.
PB - IOS Press
ER -