From Verification to Synthesis

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


Model checking methods are used to verify the correctness of digital circuits and code against their formal specification. In case of design or programming errors, they provide counterexample evidence of erroneous behavior. Model checking techniques suffer from inherent high complexity. New model checking methods attempt to speed it up and reduce the memory requirement. Recently, the more ambitious task of converting the formal specification automatically into correct-by-design code has gained significant progress. In this paper, automata-based techniques for model checking and automatic synthesis are described.
Original languageEnglish
Title of host publicationDependable Software Systems Engineering
EditorsA. Pretschner, D. Peled, M. Irlbeck
PublisherIOS Press
Number of pages14
ISBN (Electronic)978-1-61499-495-4
ISBN (Print)978-1-61499-494-7
StatePublished - 2015

Publication series

NameNATO Science for Peace and Security Series - D: Information and Communication Security


Dive into the research topics of 'From Verification to Synthesis'. Together they form a unique fingerprint.

Cite this