From falsification to verification

Doron Peled, Amir Pnueli, Lenore Zuck

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

37 Scopus citations

Abstract

This paper enhances the linear temporal logic model checking process with the ability to automatically generate a deductive proof that the system meets its temporal specification. Thus, we emphasize the point of view that model checking can also be used to justify why the system actually works. We show that, by exploiting the information in the graph that is generated during a failed search for counterexamples, we can generate a fully deductive proof that the system meets its specification.

Original languageEnglish
Title of host publicationFST TCS 2001
Subtitle of host publicationFoundations of Software Technology and Theoretical Computer Science - 21st Conference, Proceedings
EditorsRamesh Hariharan, V. Vinay, Madhavan Mukund
PublisherSpringer Verlag
Pages292-304
Number of pages13
ISBN (Print)3540430024
DOIs
StatePublished - 2001
Externally publishedYes
Event21st Conference on Foundations of Software Technology and Theoretical Computer Science, FST TCS 2001 - Bangalore, India
Duration: 13 Dec 200115 Dec 2001

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2245
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference21st Conference on Foundations of Software Technology and Theoretical Computer Science, FST TCS 2001
Country/TerritoryIndia
CityBangalore
Period13/12/0115/12/01

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 2001.

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