Abstract
This paper enhances the linear temporal logic model checking process with the ability to automatically generate a deductive proof that the system meets its temporal specification. Thus, we emphasize the point of view that model checking can also be used to justify why the system actually works. We show that, by exploiting the information in the graph that is generated during a failed search for counterexamples, we can generate a fully deductive proof that the system meets its specification.
Original language | English |
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Title of host publication | FST TCS 2001 |
Subtitle of host publication | Foundations of Software Technology and Theoretical Computer Science - 21st Conference, Proceedings |
Editors | Ramesh Hariharan, V. Vinay, Madhavan Mukund |
Publisher | Springer Verlag |
Pages | 292-304 |
Number of pages | 13 |
ISBN (Print) | 3540430024 |
DOIs | |
State | Published - 2001 |
Externally published | Yes |
Event | 21st Conference on Foundations of Software Technology and Theoretical Computer Science, FST TCS 2001 - Bangalore, India Duration: 13 Dec 2001 → 15 Dec 2001 |
Publication series
Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 2245 |
ISSN (Print) | 0302-9743 |
ISSN (Electronic) | 1611-3349 |
Conference
Conference | 21st Conference on Foundations of Software Technology and Theoretical Computer Science, FST TCS 2001 |
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Country/Territory | India |
City | Bangalore |
Period | 13/12/01 → 15/12/01 |
Bibliographical note
Publisher Copyright:© Springer-Verlag Berlin Heidelberg 2001.