Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elements in static or dynamic mode, it is possible to significantly improve performance at the cost of a limited increase in energy consumption, and vice versa. In this letter, for the first time, we design, fabricate in a commercial 16-nm FinFET process, and evaluate in silicon FlexDML, an adaptively configurable arithmetic unit. FlexDML comprises several DMLBricks, 2\× 2 and 4\× 4 DML-based multiplier units, as well as DML-based shifters and adders. FlexDML is capable of performing several arithmetic operations with flexible wordlength, such as N\× N-bit, two (N/2)\× N-bit or N\× (N/2)-bit, four (N/2)\× (N/2)-bit, and so on multiplications, as well as shifts and inner product calculations. All DMLBricks can be operational at the same time, increasing the hardware utilization to the level unattainable in typical designs that support variable wordlength. FlexDML is the first to support a pipeline multimode, where the DML mode is set separately for each pipeline stage, thus enabling more flexible ED optimization. FlexDML achieves up to 41% performance improvement in dynamic mode, and power savings of about 23% in static mode, compared to CMOS implementation.
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© 2018 IEEE.
- configurable computing
- dual mode logic (DML)