TY - JOUR

T1 - FlexDML

T2 - High Utilization Configurable Multimode Arithmetic Units Featuring Dual Mode Logic

AU - Stanger, Inbal

AU - Shavit, Netanel

AU - Taco, Ramiro

AU - Lanuzza, Marco

AU - Yavits, Leonid

AU - Levi, Itamar

AU - Fish, Alexander

N1 - Publisher Copyright:
© 2018 IEEE.

PY - 2023

Y1 - 2023

N2 - Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elements in static or dynamic mode, it is possible to significantly improve performance at the cost of a limited increase in energy consumption, and vice versa. In this letter, for the first time, we design, fabricate in a commercial 16-nm FinFET process, and evaluate in silicon FlexDML, an adaptively configurable arithmetic unit. FlexDML comprises several DMLBricks, 2\× 2 and 4\× 4 DML-based multiplier units, as well as DML-based shifters and adders. FlexDML is capable of performing several arithmetic operations with flexible wordlength, such as N\× N-bit, two (N/2)\× N-bit or N\× (N/2)-bit, four (N/2)\× (N/2)-bit, and so on multiplications, as well as shifts and inner product calculations. All DMLBricks can be operational at the same time, increasing the hardware utilization to the level unattainable in typical designs that support variable wordlength. FlexDML is the first to support a pipeline multimode, where the DML mode is set separately for each pipeline stage, thus enabling more flexible ED optimization. FlexDML achieves up to 41% performance improvement in dynamic mode, and power savings of about 23% in static mode, compared to CMOS implementation.

AB - Dual mode logic (DML) enables flexible energy-delay (ED) optimization. By setting the design elements in static or dynamic mode, it is possible to significantly improve performance at the cost of a limited increase in energy consumption, and vice versa. In this letter, for the first time, we design, fabricate in a commercial 16-nm FinFET process, and evaluate in silicon FlexDML, an adaptively configurable arithmetic unit. FlexDML comprises several DMLBricks, 2\× 2 and 4\× 4 DML-based multiplier units, as well as DML-based shifters and adders. FlexDML is capable of performing several arithmetic operations with flexible wordlength, such as N\× N-bit, two (N/2)\× N-bit or N\× (N/2)-bit, four (N/2)\× (N/2)-bit, and so on multiplications, as well as shifts and inner product calculations. All DMLBricks can be operational at the same time, increasing the hardware utilization to the level unattainable in typical designs that support variable wordlength. FlexDML is the first to support a pipeline multimode, where the DML mode is set separately for each pipeline stage, thus enabling more flexible ED optimization. FlexDML achieves up to 41% performance improvement in dynamic mode, and power savings of about 23% in static mode, compared to CMOS implementation.

KW - Arithmetic

KW - CMOS

KW - DML

KW - configurable computing

KW - dual mode logic (DML)

KW - dynamic

KW - mixed-mode

KW - pipeline

KW - static

UR - http://www.scopus.com/inward/record.url?scp=85151530737&partnerID=8YFLogxK

U2 - 10.1109/LSSC.2023.3259102

DO - 10.1109/LSSC.2023.3259102

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AN - SCOPUS:85151530737

SN - 2573-9603

VL - 6

SP - 73

EP - 76

JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -