First order temporal logic monitoring with BDDs

Klaus Havelund; Doron Peled; Dogan Ulus

doi:10.23919/fmcad.2017.8102249

First order temporal logic monitoring with BDDs

Klaus Havelund, Doron Peled, Dogan Ulus

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

45 Scopus citations

Abstract

Runtime verification is aimed at analyzing execution traces stemming from a running program or system. The traditional purpose is to detect the lack of conformance with respect to a formal specification. Numerous efforts in the field have focused on monitoring so-called parametric specifications, where events carry data, and formulas can refer to such. Since a monitor for such specifications has to store observed data, the challenge is to have an efficient representation and manipulation of Boolean operators, quantification, and lookup of data. The fundamental problem is that the actual values of the data are not necessarily bounded or provided in advance. In this work we explore the use of Binary Decision Diagrams (BDDs) for representing observed data. Our experiments show a substantial improvement in performance compared to related work.

Original language	English
Title of host publication	Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017
Editors	Georg Weissenbacher, Daryl Stewart
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	116-123
Number of pages	8
ISBN (Electronic)	9780983567875
DOIs	https://doi.org/10.23919/fmcad.2017.8102249
State	Published - 8 Nov 2017
Event	17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017 - Vienna, Austria Duration: 2 Oct 2017 → 6 Oct 2017

Publication series

Name	Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017

Conference

Conference	17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017
Country/Territory	Austria
City	Vienna
Period	2/10/17 → 6/10/17

Bibliographical note

Publisher Copyright:
© 2017 FMCAD Inc.

Funding

The research performed by the first author was carried out at Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration. The research performed by the second author was partially funded by Israeli Science Foundation grant 2239/15: "Runtime Measuring and Checking of Cyber Physical Systems".

Funders	Funder number
National Aeronautics and Space Administration
Israel Science Foundation	2239/15

Access to Document

10.23919/fmcad.2017.8102249

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Havelund, K., Peled, D., & Ulus, D. (2017). First order temporal logic monitoring with BDDs. In G. Weissenbacher, & D. Stewart (Eds.), Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017 (pp. 116-123). Article 8102249 (Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/fmcad.2017.8102249

Havelund, Klaus ; Peled, Doron ; Ulus, Dogan. / First order temporal logic monitoring with BDDs. Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017. editor / Georg Weissenbacher ; Daryl Stewart. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 116-123 (Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017).

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Havelund, K, Peled, D & Ulus, D 2017, First order temporal logic monitoring with BDDs. in G Weissenbacher & D Stewart (eds), Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017., 8102249, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017, Institute of Electrical and Electronics Engineers Inc., pp. 116-123, 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017, Vienna, Austria, 2/10/17. https://doi.org/10.23919/fmcad.2017.8102249

First order temporal logic monitoring with BDDs. / Havelund, Klaus; Peled, Doron; Ulus, Dogan.
Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017. ed. / Georg Weissenbacher; Daryl Stewart. Institute of Electrical and Electronics Engineers Inc., 2017. p. 116-123 8102249 (Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Havelund K, Peled D, Ulus D. First order temporal logic monitoring with BDDs. In Weissenbacher G, Stewart D, editors, Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 116-123. 8102249. (Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017). doi: 10.23919/fmcad.2017.8102249

First order temporal logic monitoring with BDDs

Abstract

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Bibliographical note

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