FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture

Esteban Garzon, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Associative access is widely used in fundamental microarchitectural components, such as caches and TLBs. However, associative (or content addressable) memories (CAMs) have been traditionally considered too large, too energy-hungry, and not scalable, and therefore, have limited use in modern computer microarchitecture. This work revisits these presumptions and proposes an energy-efficient fully-associative tag array (FASTA) architecture, based on a novel complementary CAM (CCAM) bitcell. CCAM offers a full CMOS solution for CAM, removing the need for time- and energy-consuming precharge and combining the speed of NOR CAM and low energy consumption of NAND CAM. While providing better performance and energy consumption, CCAM features a larger area compared to state-of-the-art CAM designs. We further show how FASTA can be used to construct a novel aliasing-free, energy-efficient, Very-Many-Way Associative (VMWA) cache. Circuit-level simulations using 16 nm FinFET technology show that a 128 kB FASTA-based 256-way 8-set associative cache is 28% faster and consumes 88% less energy-per-access than a same sized 8-way (256-set) SRAM based cache, while also providing aliasing-free operation. System-level evaluation performed on the Sniper simulator shows that the VMWA cache exhibits lower Misses Per Kilo Instructions (MPKI) for the majority of benchmarks. Specifically, the 256-way associative cache achieves 17.3%, 11.5%, and 1.2% lower average MPKI for L1, L2, and L3 caches, respectively, compared to a 16-way associative cache. The average IPC improvement for L1, L2, and L3 caches are 1.6%, 1.4%, and 0.2%, respectively.

Original languageEnglish
Pages (from-to)13923-13943
Number of pages21
JournalIEEE Access
Volume12
DOIs
StatePublished - 2024

Bibliographical note

Publisher Copyright:
© 2013 IEEE.

Funding

This work was supported in part by the European Union’s Horizon Europe Program for Research and Innovation under Grant 101047160, in part by the Israeli Ministry of Science and Technology under Lise Meitner grant for Israeli-Swedish Research Collaboration under Grant 1001569396, and in part by the Israeli Ministry of Science and Technology grant for Groundbreaking Research under Grant 1001702600. The work of Esteban Garzón was supported by the Italian Ministry for Universities and Research (MUR) under the Call ‘‘Horizon Europe 2021–2027 Program under Grant H25F21001420001’’

FundersFunder number
European Union’s Horizon Europe Program for Research and Innovation101047160
Ministero dell’Istruzione, dell’Università e della RicercaH25F21001420001
Ministry of science and technology, Israel1001569396, 1001702600

    Keywords

    • 256-way associative cache
    • CAM
    • Fully associative cache
    • aliasing
    • associative memory
    • content addressable memory
    • memory architecture

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