Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications

Esteban Garzon; Raffaele De Rose; Felice Crupi; Adam Teman; Marco Lanuzza

doi:10.1109/TNANO.2021.3049694

Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications

Esteban Garzon
, Raffaele De Rose
, Felice Crupi
, Adam Teman
, Marco Lanuzza

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

University of Calabria
Bar-Ilan University

Research output: Contribution to journal › Article › peer-review

29 Scopus citations

Abstract

This paper evaluates the potential of spin-transfer torque magnetic random-access memories (STT-MRAMs) operating at cryogenic temperatures. Our study was carried out at both circuit and architecture levels by exploiting experimental magnetic tunnel junction (MTJ) data and a CMOS technology that was fully characterized down to 77 K. As a main result of our analysis, we show that for medium to large sized cache architectures, STT-MRAMs outperform their six-transistor static random access memory (6T-SRAM) counterparts at 77 K in terms of both dynamic and static (leakage) power as well as read access latency, only underperforming in terms of write latency. For an 8 MB STT-MRAM cache, the read latency is improved by 2× along with a reduction of 45% and 30% in read and write energy, respectively, as compared to an SRAM implementation.

Original language	English
Article number	9316299
Pages (from-to)	123-128
Number of pages	6
Journal	IEEE Transactions on Nanotechnology
Volume	20
DOIs	https://doi.org/10.1109/TNANO.2021.3049694
State	Published - 2021

Bibliographical note

Publisher Copyright:
© 2002-2012 IEEE.

Funding

Manuscript received October 15, 2020; accepted December 29, 2020. Date of publication January 6, 2021; date of current version February 1, 2021. This work was supported in part by the Israel Innovation Authority under the Smart Imaging consortium, in part by the Israel Science Foundation under Grant 996/18, and in part by under the Grant 2019-1-U.0. (“diodi spintronici rad-hard ad elevata sensitivitá - DIOSPIN”) funded by the Italian Space Agency (ASI) within the call “Nuove idee per la componentistica spaziale del futuro”. The work of Esteban Garzón was supported by a Sandwich program grant of the Israeli Council for Higher Education. The review of this paper was arranged by Associate Editor P.-E. Gaillardon. (Corresponding author: Esteban Garzón.) Esteban Garzón is with the Department of Computer Engineering, Modeling, Electronics and Systems (DIMES), University of Calabria, 87036 Rende, Italy and also with the EnICS Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: [email protected]).

Funders	Funder number
Council for Higher Education
Agenzia Spaziale Italiana
Agenzia Spaziale Italiana
Israel Science Foundation	996/18, 2019-1-U.0
Israel Innovation Authority

Keywords

77 K
STT-MRAM
cache memory
cold computing
cryogenic

Access to Document

10.1109/TNANO.2021.3049694

Cite this

@article{35da50fe4697494aa163621946b1a5e0,

title = "Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications",

abstract = "This paper evaluates the potential of spin-transfer torque magnetic random-access memories (STT-MRAMs) operating at cryogenic temperatures. Our study was carried out at both circuit and architecture levels by exploiting experimental magnetic tunnel junction (MTJ) data and a CMOS technology that was fully characterized down to 77 K. As a main result of our analysis, we show that for medium to large sized cache architectures, STT-MRAMs outperform their six-transistor static random access memory (6T-SRAM) counterparts at 77 K in terms of both dynamic and static (leakage) power as well as read access latency, only underperforming in terms of write latency. For an 8 MB STT-MRAM cache, the read latency is improved by 2× along with a reduction of 45\% and 30\% in read and write energy, respectively, as compared to an SRAM implementation.",

keywords = "77 K, STT-MRAM, cache memory, cold computing, cryogenic",

author = "Esteban Garzon and \{De Rose\}, Raffaele and Felice Crupi and Adam Teman and Marco Lanuzza",

note = "Publisher Copyright: {\textcopyright} 2002-2012 IEEE.",

year = "2021",

doi = "10.1109/TNANO.2021.3049694",

language = "אנגלית",

volume = "20",

pages = "123--128",

journal = "IEEE Transactions on Nanotechnology",

issn = "1536-125X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications

AU - Garzon, Esteban

AU - De Rose, Raffaele

AU - Crupi, Felice

AU - Teman, Adam

AU - Lanuzza, Marco

PY - 2021

Y1 - 2021

N2 - This paper evaluates the potential of spin-transfer torque magnetic random-access memories (STT-MRAMs) operating at cryogenic temperatures. Our study was carried out at both circuit and architecture levels by exploiting experimental magnetic tunnel junction (MTJ) data and a CMOS technology that was fully characterized down to 77 K. As a main result of our analysis, we show that for medium to large sized cache architectures, STT-MRAMs outperform their six-transistor static random access memory (6T-SRAM) counterparts at 77 K in terms of both dynamic and static (leakage) power as well as read access latency, only underperforming in terms of write latency. For an 8 MB STT-MRAM cache, the read latency is improved by 2× along with a reduction of 45% and 30% in read and write energy, respectively, as compared to an SRAM implementation.

AB - This paper evaluates the potential of spin-transfer torque magnetic random-access memories (STT-MRAMs) operating at cryogenic temperatures. Our study was carried out at both circuit and architecture levels by exploiting experimental magnetic tunnel junction (MTJ) data and a CMOS technology that was fully characterized down to 77 K. As a main result of our analysis, we show that for medium to large sized cache architectures, STT-MRAMs outperform their six-transistor static random access memory (6T-SRAM) counterparts at 77 K in terms of both dynamic and static (leakage) power as well as read access latency, only underperforming in terms of write latency. For an 8 MB STT-MRAM cache, the read latency is improved by 2× along with a reduction of 45% and 30% in read and write energy, respectively, as compared to an SRAM implementation.

KW - 77 K

KW - STT-MRAM

KW - cache memory

KW - cold computing

KW - cryogenic

UR - https://www.scopus.com/pages/publications/85099183206

U2 - 10.1109/TNANO.2021.3049694

DO - 10.1109/TNANO.2021.3049694

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:85099183206

SN - 1536-125X

VL - 20

SP - 123

EP - 128

JO - IEEE Transactions on Nanotechnology

JF - IEEE Transactions on Nanotechnology

M1 - 9316299

ER -

Exploiting STT-MRAMs for Cryogenic Non-Volatile Cache Applications

Abstract

Bibliographical note

Funding

Keywords

Access to Document

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