Abstract
In this paper we evaluate the implementation options of energy-efficient dual mode logic (DML) circuits in 28nm fully depleted silicon-on-insulator (FD-SOI) technology. The combination of the flexibility of Dual Mode Logic (DML) and the unique characteristics of the FD-SOI technology has enormous potential to design energy-efficient adaptive digital circuits operating on an ultra-wide voltage range. As a main result, we demonstrate that single well option offered by the FD-SOI greatly extends the low-granularity energy-delay (ED) optimization capability of DML-based designs. By exploiting the above implementation strategy, a 16-bit DML carry skip adder reduces its energy consumption by 41% and increases its speed of about 26% when changing its operation mode (from static to dynamic) at 0.4V as compared to its equivalent standard CMOS design.
Original language | English |
---|---|
Title of host publication | 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728133201 |
State | Published - 2020 |
Event | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
---|---|
Volume | 2020-October |
ISSN (Print) | 0271-4310 |
Conference
Conference | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 |
---|---|
City | Virtual, Online |
Period | 10/10/20 → 21/10/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE
Funding
ACKNOWLEDGMENT This work was supported by the Golda Meir scholarship of the Israel Ministry of Science.
Funders | Funder number |
---|---|
Israel Ministry of Science |
Keywords
- Adaptive energy-efficient digital design
- Dual mode logic
- FD-SOI