Abstract
This paper explores STT-MRAM bitcells based on double-barrier magnetic tunnel junctions (DMTJs) at the circuit-level, benchmarking TFET - against FinFET-based bitcells focusing on their write operation. Different bitcell configurations are tested to find optimal minimum energy design points using both technologies in a range of ultralow supply voltages. TFETs were found to be the optimal access device for supply voltages under or equal to 0.4V because of their significantly more robust behavior and lower write energy consumption, albeit higher write delays and bigger area for higher voltages.
| Original language | English |
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| Title of host publication | 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781665420082 |
| DOIs | |
| State | Published - 2022 |
| Externally published | Yes |
| Event | 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 - Santiago, Chile Duration: 1 Mar 2022 → 4 Mar 2022 |
Publication series
| Name | 2022 IEEE 13th Latin American Symposium on Circuits and Systems, LASCAS 2022 |
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Conference
| Conference | 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022 |
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| Country/Territory | Chile |
| City | Santiago |
| Period | 1/03/22 → 4/03/22 |
Bibliographical note
Publisher Copyright:© 2022 IEEE.
Keywords
- FinFET
- STT-MRAM
- double-barrier magnetic tunnel junction (DMTJ)
- tunnel FET (TFET)
- ultralow voltage