Abstract
While adders are usually designed for the worst-case where their carry propagates through the entire bits, those cases rarely happen at real operation. This work takes advantage of the infrequent worst-case occurrences by designing adders for the average-case. Such design implies that computation errors may happen. Those are being corrected by implementing multi-mode addition with the aid of a dedicated control circuit. A power-delay-energy model is presented, enabling to find the optimal design point. We show that for cases where the systems critical paths are dictated by the adders, the systems operation voltage can be scaled, without harming the clock cycle and with very small performance degradation. For an adder per-se, potential energy savings of up to 50% is shown. The multi-mode adder has been integrated in a 32-bit pipelined MIPS processor, validating the correctness of such design approach.
| Original language | English |
|---|---|
| Pages (from-to) | 176-182 |
| Number of pages | 7 |
| Journal | Integration, the VLSI Journal |
| Volume | 55 |
| DOIs | |
| State | Published - 1 Sep 2016 |
Bibliographical note
Publisher Copyright:© 2016 Elsevier B.V.
Funding
The authors are grateful to M. Doron, E. Aberbach and O. Cohen of Bar-Ilan University for the design and implementation of the MIPS processor. They are also thankful to the anonymous referees for their useful comments. This work was supported by the Israeli Chief Scientist MAGNET program, HiPer Consortium.
| Funders | Funder number |
|---|---|
| Chief Scientist Office |
Keywords
- Adders
- Inaccurate computing
- Low-power design
- Multi-mode adders
- Voltage scaling