TY - GEN
T1 - Energy-Delay Tradeoffs of Low-Voltage Dual Mode Logic in 28nm FD-SOI
AU - Fish, A.
AU - Lanuzza, M.
AU - Levi, I.
AU - Taco, R.
N1 - Place of conference:USA
PY - 2017
Y1 - 2017
N2 - In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.
AB - In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.
UR - https://ieeexplore.ieee.org/abstract/document/8309250/authors#authors
M3 - Conference contribution
BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
PB - IEEE
ER -