Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

Ramiro Taco; Itamar Levi; Marco Lanuzza; Alexander Fish

doi:10.1109/s3s.2017.8309250

Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish

University of Calabria

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.

Original language	English
Title of host publication	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538637654
DOIs	https://doi.org/10.1109/s3s.2017.8309250
State	Published - 2 Jul 2017
Event	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States Duration: 16 Oct 2017 → 18 Oct 2017

Publication series

Name	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume	2018-March

Conference

Conference	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/Territory	United States
City	Burlingame
Period	16/10/17 → 18/10/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

Funding

The authors acknowledge the Israel Science Foundation (ISF) for financial support (grant 1678/13).

Funders	Funder number
Israel Science Foundation	1678/13

Keywords

Dual mode logic (DML)
carry skip adder
low-voltage

Access to Document

10.1109/s3s.2017.8309250

Cite this

Taco, R., Levi, I., Lanuzza, M., & Fish, A. (2017). Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (pp. 1-3). (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/s3s.2017.8309250

@inproceedings{b5be3f334b2742a5a3072b4d9330dc01,

title = "Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI",

abstract = "In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.",

keywords = "Dual mode logic (DML), carry skip adder, low-voltage",

author = "Ramiro Taco and Itamar Levi and Marco Lanuzza and Alexander Fish",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 ; Conference date: 16-10-2017 Through 18-10-2017",

year = "2017",

month = jul,

day = "2",

doi = "10.1109/s3s.2017.8309250",

language = "אנגלית",

series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1--3",

booktitle = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

address = "ארצות הברית",

}

Taco, R, Levi, I, Lanuzza, M & Fish, A 2017, Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 16/10/17. https://doi.org/10.1109/s3s.2017.8309250

Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI. / Taco, Ramiro; Levi, Itamar; Lanuzza, Marco et al.
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

AU - Taco, Ramiro

AU - Levi, Itamar

AU - Lanuzza, Marco

AU - Fish, Alexander

PY - 2017/7/2

Y1 - 2017/7/2

N2 - In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.

AB - In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.

KW - Dual mode logic (DML)

KW - carry skip adder

KW - low-voltage

UR - http://www.scopus.com/inward/record.url?scp=85047752674&partnerID=8YFLogxK

U2 - 10.1109/s3s.2017.8309250

DO - 10.1109/s3s.2017.8309250

M3 - ???researchoutput.researchoutputtypes.contributiontobookanthology.conference???

AN - SCOPUS:85047752674

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 3

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -

Energy-delay tradeoffs of low-voltage dual mode logic in 28nm FD-SOI

Abstract

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Bibliographical note

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Keywords

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