Enabling full associativity with memristive address decoder

Leonid Yavits; Roman Kaplan; Ran Ginosar

doi:10.1109/mm.2018.053631139

Enabling full associativity with memristive address decoder

Leonid Yavits, Roman Kaplan, Ran Ginosar

Technion-Israel Institute of Technology

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

Address decoders are typically built using regular logic gates. A novel Memristive Perfect Induction gate replaces standard NAND, allowing for storing the address alongside data and comparing it to the input address, thus transforming the address decoder into CAM and enabling fully associative access. Applications include fully associative TLB, cache, and virtually addressable memory.

Original language	English
Article number	8474950
Pages (from-to)	32-40
Number of pages	9
Journal	IEEE Micro
Volume	38
Issue number	5
DOIs	https://doi.org/10.1109/mm.2018.053631139
State	Published - 1 Sep 2018
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1981-2012 IEEE.

Keywords

M\memory control and access
cache memories
content addressable memory
emerging technologies
hardware
memory hierarchy
virtual memory

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10.1109/mm.2018.053631139

Cite this

@article{19ef6894c7a94fee9003d06eb330abc5,

title = "Enabling full associativity with memristive address decoder",

abstract = "Address decoders are typically built using regular logic gates. A novel Memristive Perfect Induction gate replaces standard NAND, allowing for storing the address alongside data and comparing it to the input address, thus transforming the address decoder into CAM and enabling fully associative access. Applications include fully associative TLB, cache, and virtually addressable memory.",

keywords = "M\memory control and access, cache memories, content addressable memory, emerging technologies, hardware, memory hierarchy, virtual memory",

author = "Leonid Yavits and Roman Kaplan and Ran Ginosar",

note = "Publisher Copyright: {\textcopyright} 1981-2012 IEEE.",

year = "2018",

month = sep,

day = "1",

doi = "10.1109/mm.2018.053631139",

language = "אנגלית",

volume = "38",

pages = "32--40",

journal = "IEEE Micro",

issn = "0272-1732",

publisher = "IEEE Computer Society",

number = "5",

}

TY - JOUR

T1 - Enabling full associativity with memristive address decoder

AU - Yavits, Leonid

AU - Kaplan, Roman

AU - Ginosar, Ran

PY - 2018/9/1

Y1 - 2018/9/1

N2 - Address decoders are typically built using regular logic gates. A novel Memristive Perfect Induction gate replaces standard NAND, allowing for storing the address alongside data and comparing it to the input address, thus transforming the address decoder into CAM and enabling fully associative access. Applications include fully associative TLB, cache, and virtually addressable memory.

AB - Address decoders are typically built using regular logic gates. A novel Memristive Perfect Induction gate replaces standard NAND, allowing for storing the address alongside data and comparing it to the input address, thus transforming the address decoder into CAM and enabling fully associative access. Applications include fully associative TLB, cache, and virtually addressable memory.

KW - M\memory control and access

KW - cache memories

KW - content addressable memory

KW - emerging technologies

KW - hardware

KW - memory hierarchy

KW - virtual memory

UR - http://www.scopus.com/inward/record.url?scp=85054543958&partnerID=8YFLogxK

U2 - 10.1109/mm.2018.053631139

DO - 10.1109/mm.2018.053631139

M3 - ???researchoutput.researchoutputtypes.contributiontojournal.article???

AN - SCOPUS:85054543958

SN - 0272-1732

VL - 38

SP - 32

EP - 40

JO - IEEE Micro

JF - IEEE Micro

IS - 5

M1 - 8474950

ER -

Enabling full associativity with memristive address decoder

Abstract

Bibliographical note

Keywords

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