Enabling full associativity with memristive address decoder

Leonid Yavits; Roman Kaplan; Ran Ginosar

doi:10.1109/MM.2018.053631139

Enabling full associativity with memristive address decoder

Leonid Yavits, Roman Kaplan, Ran Ginosar

Research output: Contribution to journal › Article › peer-review

Abstract

Address decoders are typically built using regular logic gates. A novel Memristive Perfect Induction gate replaces standard NAND, allowing for storing the address alongside data and comparing it to the input address, thus transforming the address decoder into CAM and enabling fully associative access. Applications include fully associative TLB, cache, and virtually addressable memory.

Original language	English
Article number	8474950
Pages (from-to)	32-40
Number of pages	9
Journal	IEEE Micro
Volume	38
Issue number	5
DOIs	https://doi.org/10.1109/MM.2018.053631139
State	Published - 1 Sep 2018
Externally published	Yes

Bibliographical note

Publisher Copyright:
© 1981-2012 IEEE.

Keywords

M\memory control and access
cache memories
content addressable memory
emerging technologies
hardware
memory hierarchy
virtual memory

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10.1109/MM.2018.053631139

Cite this

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Enabling full associativity with memristive address decoder

Abstract

Bibliographical note

Keywords

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