Abstract
Information leakage through physical channels is a major hurdle in embedded hardware security. This paper overviews the three key factors in the embedded hardware security space, focusing on gray-box (bounded resources) power analysis attacks: The adversary's knowledge and abilities, the security metrics used by adversaries' and security evaluators and gate-level countermeasures. A new design paradigm, dubbed pAsynch, that utilizes internal signals and random signals to uniformly spread the information-carrying energy within the clock period in a specific way with a resolution below the band-width and noise-filtering abilities of advanced measurement equipment is introduced. The advantages and design challenges introduced by the pAsynch paradigm are discussed.
Original language | English |
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Title of host publication | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 395-400 |
Number of pages | 6 |
ISBN (Electronic) | 9783981926316 |
DOIs | |
State | Published - 19 Apr 2018 |
Event | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany Duration: 19 Mar 2018 → 23 Mar 2018 |
Publication series
Name | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
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Volume | 2018-January |
Conference
Conference | 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
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Country/Territory | Germany |
City | Dresden |
Period | 19/03/18 → 23/03/18 |
Bibliographical note
Publisher Copyright:© 2018 EDAA.
Keywords
- hardware security
- information leakage
- pAsynch
- pseudo asynchronous
- side channel