Efficient Implementation of Punctured Parallel Finite Field Multipliers

Yaara Neumeier, Yehoshua Pesso, Osnat Keren

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Finite field multipliers are embedded in many applications. In some applications, e.g., in cryptographic primitives protected by security oriented codes, only r bits out of the m-bit product are required. In such cases, the circuit area can be significantly reduced by implementing a punctured finite field multiplier. This article deals with efficient implementation of multipliers. It is shown that the number of binary operations (equivalently, the number of gates) depends on both the chosen irreducible polynomial that defines the finite field and the indices of the r coordinates that are computed. Upper and lower bounds are presented on the implementation cost of punctured multipliers over a finite field defined by an irreducible trinomial, and a set of r coordinates that achieves the lower bound is itemized.

Original languageEnglish
Article number7229372
Pages (from-to)2260-2267
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number9
StatePublished - 1 Sep 2015

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.


  • Digital arithmetic
  • Finite field multiplier
  • Galois field
  • Multiplying circuit


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