Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach

Keyphrases

• 65nm CMOS 25%
• Access Time 25%
• Art Design 25%
• Cell-based 25%
• Consumption Area 25%
• Design Flow 25%
• Design Methodology 25%
• Design Tools 25%
• Efficient Implementation 100%
• Greatest Difficulty 25%
• High-performance Parallel Computing 25%
• High-speed Performance 25%
• Implementation Approach 25%
• Implementation Results 25%
• Leakage Power 50%
• Memory Approach 100%
• Multi-port Memory 25%
• Novel Methodology 25%
• Performance Standards 25%
• Physical Implementation 75%
• Placement Density 25%
• Power Consumption 25%
• Power Performance 25%
• Process Standards 25%
• Processing Node 25%
• Read Port 50%
• Read Power 25%
• Register File 25%
• Regular Structure 25%
• Salamandra Salamandra 25%
• Standard Cell Library 25%
• Standard Cell Memory 100%
• Utility-based 25%
• Wiring 25%
• Write Power 50%

Engineering

• Access Time 33%
• Design Flow 33%
• Design Tool 33%
• Efficient Implementation 100%
• Electric Power Utilization 33%
• Extreme Case 33%
• Multiplicity 33%
• Nodes 33%
• Performance Standard 33%
• Physical Implementation 100%
• Port Register 33%
• Register File 33%

Computer Science

• And-States 33%
• Area Power Consumption 33%
• Efficient Implementation 100%
• Multiplicity 33%
• Open Source 33%
• Parallel Computation 33%
• Performance Standard 33%
• Physical Implementation 100%