Abstract
We present efficient Dense and Sparse Matrix Multiplication on GP-SIMD, a hybrid general purpose SIMD computer architecture that eliminates synchronization by in-memory computing, combining data storage and massively parallel processing. Cycle-accurate simulation of on a large set of matrices shows enhanced power efficiency relative to conventional architectures.
Original language | English |
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Title of host publication | 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781479954124 |
DOIs | |
State | Published - 10 Nov 2014 |
Externally published | Yes |
Event | 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 - Palma de Mallorca, Spain Duration: 29 Sep 2014 → 1 Oct 2014 |
Publication series
Name | 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 |
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Conference
Conference | 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 |
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Country/Territory | Spain |
City | Palma de Mallorca |
Period | 29/09/14 → 1/10/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
Keywords
- Associative Processor
- GP-SIMD
- In-Memory Computing
- Memory Intensive Computing
- Sparse Linear Algebra