Effects on Circular Enclosed Gate Device with Base Model and Varying Geometry Condition and Parameters

Study aims at devising a enhance performance driven Circular Enclosed Gate (CEG) MOSFET's from Model 1 to Model 3, with focus on maintaining power efficiency. Starting with Model 1, subsequent iteration introduced the optimized geometric structure addressing trade-offs in short channel effects, leakage currents, and switching speed, while balancing design and low threshold voltages (V_TH: 0.13 V for NMOS, 0.1 V for PMOS). In Model 2(a), improved performance was seen with increase in drain radius, which enhancing the I_ON/I_OFF ratio. In contrast Model 2(b) demonstrated a better overall efficiency, by optimizing the source-drain geometry for lower Drain-Induced Barrier Lowering (DIBL) and improved subthreshold slopes. Meanwhile with compact design Model 3 achieves an impressive I_ON/I_OFF ratio of 1.15×10⁹, and exceptionally low leakage currents (I_OFF: 1.40×10^-12 A for NMoS) making it highly suitable for energy-efficient and reliable applications. This step-by-step refinement underscores the potential for continuous advancements in CEG MoSFETs, driving the evolution of next-generation CMoS technology.