Abstract
After analyzing the impacts of sampling frequency offset on the performance of orthogonal frequency division multiplexing (OFDM) systems, a new sampling frequency synchronization algorithm in frequency domain was proposed and its mathematical analysis was presented. This algorithm was optimized to be easy for hardware implementation, and obtained 20% reduction in logic gates and double speed than the algorithm using least square (LS) method. Matlab simulations were conducted on an 802.11a system platform. Simulation showed that this algorithm worked effectively and fulfilled the standard requirements in both the additive white Gaussian noise (AWGN) channel and the multi-patch channel. The algorithm was successfully implemented on an 802.11a field programmable gate array (FPGA) platform. On-chip real-time analysis of the algorithm using Xilinx Chipscope Pro demonstrate that this algorithm can work efficiently and effectively as a block of an OFDM baseband receiver processor.
| Original language | English |
|---|---|
| Pages (from-to) | 935-940 |
| Number of pages | 6 |
| Journal | Zhejiang Daxue Xuebao (Gongxue Ban)/Journal of Zhejiang University (Engineering Science) |
| Volume | 41 |
| Issue number | 6 |
| State | Published - Jun 2007 |
| Externally published | Yes |
Keywords
- 802.11a
- Field programmable gate array (FPGA)
- Orthogonal frequency division multiplexing (OFDM)
- Sampling frequency synchronization