DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

A. Teman, J. Constantin, A. Bonetti, C. Müller, L. Schmid, A. Burg

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.
Original languageAmerican English
Title of host publicationESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
StatePublished - 2016

Bibliographical note

Place of conference:Lausanne, Switzerland


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