DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

Jeremy Constantin; Andrea Bonetti; Adam Teman; Christoph Müller; Lorenz Schmid; Andreas Burg

doi:10.1109/ESSCIRC.2016.7598292

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

Jeremy Constantin, Andrea Bonetti, Adam Teman, Christoph Müller, Lorenz Schmid, Andreas Burg

Swiss Federal Institute of Technology Lausanne

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.

Original language	English
Title of host publication	ESSCIRC 2016
Subtitle of host publication	42nd European Solid-State Circuits Conference
Publisher	IEEE Computer Society
Pages	261-264
Number of pages	4
ISBN (Electronic)	9781509029723
DOIs	https://doi.org/10.1109/ESSCIRC.2016.7598292
State	Published - 18 Oct 2016
Event	42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland Duration: 12 Sep 2016 → 15 Sep 2016

Publication series

Name	European Solid-State Circuits Conference
Volume	2016-October
ISSN (Print)	1930-8833

Conference

Conference	42nd European Solid-State Circuits Conference, ESSCIRC 2016
Country/Territory	Switzerland
City	Lausanne
Period	12/09/16 → 15/09/16

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

Access to Document

10.1109/ESSCIRC.2016.7598292

Cite this

Constantin, J., Bonetti, A., Teman, A., Müller, C., Schmid, L., & Burg, A. (2016). DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. In ESSCIRC 2016: 42nd European Solid-State Circuits Conference (pp. 261-264). Article 7598292 (European Solid-State Circuits Conference; Vol. 2016-October). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2016.7598292

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title = "DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment",

abstract = "This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19\% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41\%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15\%, compared to a static clocking scheme based on worst case excitation.",

author = "Jeremy Constantin and Andrea Bonetti and Adam Teman and Christoph M{\"u}ller and Lorenz Schmid and Andreas Burg",

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Constantin, J, Bonetti, A, Teman, A, Müller, C, Schmid, L & Burg, A 2016, DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. in ESSCIRC 2016: 42nd European Solid-State Circuits Conference., 7598292, European Solid-State Circuits Conference, vol. 2016-October, IEEE Computer Society, pp. 261-264, 42nd European Solid-State Circuits Conference, ESSCIRC 2016, Lausanne, Switzerland, 12/09/16. https://doi.org/10.1109/ESSCIRC.2016.7598292

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. / Constantin, Jeremy; Bonetti, Andrea; Teman, Adam et al.
ESSCIRC 2016: 42nd European Solid-State Circuits Conference. IEEE Computer Society, 2016. p. 261-264 7598292 (European Solid-State Circuits Conference; Vol. 2016-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

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