DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

Jeremy Constantin, Andrea Bonetti, Adam Teman, Christoph Müller, Lorenz Schmid, Andreas Burg

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations


This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation.

Original languageEnglish
Title of host publicationESSCIRC 2016
Subtitle of host publication42nd European Solid-State Circuits Conference
PublisherIEEE Computer Society
Number of pages4
ISBN (Electronic)9781509029723
StatePublished - 18 Oct 2016
Event42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Switzerland
Duration: 12 Sep 201615 Sep 2016

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833


Conference42nd European Solid-State Circuits Conference, ESSCIRC 2016

Bibliographical note

Publisher Copyright:
© 2016 IEEE.


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