Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS

Oskar Andersson; Babak Mohammadi; Pascal Meinerzhagen; Andreas Burg; Joachim Neves Rodrigues

doi:10.1109/esscirc.2013.6649106

Dual-V_T 4kb sub-V_T memories with <1 pW/bit leakage in 65 nm CMOS

Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

Two standard-cell based subthreshold (sub-V_T) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-V_T storage and fill the gap of missing sub-V_T memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-V _T approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.

Original language	English
Title of host publication	ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference
Pages	197-200
Number of pages	4
DOIs	https://doi.org/10.1109/esscirc.2013.6649106
State	Published - 2013
Externally published	Yes
Event	39th European Solid-State Circuits Conference, ESSCIRC 2013 - Bucharest, Romania Duration: 16 Sep 2013 → 20 Sep 2013

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	39th European Solid-State Circuits Conference, ESSCIRC 2013
Country/Territory	Romania
City	Bucharest
Period	16/09/13 → 20/09/13

Access to Document

10.1109/esscirc.2013.6649106

Cite this

@inproceedings{6ccd107f5a1f4e3583afd87a9df356ac,

title = "Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS",

abstract = "Two standard-cell based subthreshold (sub-VT) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-V T approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.",

author = "Oskar Andersson and Babak Mohammadi and Pascal Meinerzhagen and Andreas Burg and Rodrigues, {Joachim Neves}",

year = "2013",

doi = "10.1109/esscirc.2013.6649106",

language = "אנגלית",

isbn = "9781479906437",

series = "European Solid-State Circuits Conference",

pages = "197--200",

booktitle = "ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference",

note = "39th European Solid-State Circuits Conference, ESSCIRC 2013 ; Conference date: 16-09-2013 Through 20-09-2013",

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Andersson, O, Mohammadi, B, Meinerzhagen, P, Burg, A & Rodrigues, JN 2013, Dual-V_T 4kb sub-V_T memories with <1 pW/bit leakage in 65 nm CMOS. in ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference., 6649106, European Solid-State Circuits Conference, pp. 197-200, 39th European Solid-State Circuits Conference, ESSCIRC 2013, Bucharest, Romania, 16/09/13. https://doi.org/10.1109/esscirc.2013.6649106

Dual-V_T 4kb sub-V_T memories with <1 pW/bit leakage in 65 nm CMOS. / Andersson, Oskar; Mohammadi, Babak; Meinerzhagen, Pascal et al.
ESSCIRC 2013 - Proceedings of the 39th European Solid-State Circuits Conference. 2013. p. 197-200 6649106 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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