Abstract
The recently proposed dual mode logic (DML) gates family enables a very high level of energy- delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to improve energy efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the design's critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption reduction. The proposed approach is analyzed on a 128 bit carry skip adder. Simulations, carried out in a standard 40 nm digital CMOS process with VDD D 400 mV, show that the proposed approach allows performance improvement of X2 along with reduction of energy consumption of X2.5, as compared with a standard CMOS implementation. At VDD D 1:1 V, improvements of 1.3X and 1.5X in performance and energy are achieved, respectively.
| Original language | English |
|---|---|
| Article number | 6514913 |
| Pages (from-to) | 258-265 |
| Number of pages | 8 |
| Journal | IEEE Access |
| Volume | 1 |
| DOIs | |
| State | Published - 2013 |
Bibliographical note
DBLP License: DBLP's bibliographic metadata records provided through http://dblp.org/ are distributed under a Creative Commons CC0 1.0 Universal Public Domain Dedication. Although the bibliographic metadata records are provided consistent with CC0 1.0 Dedication, the content described by the metadata records is not. Content may be subject to copyright, rights of privacy, rights of publicity and other restrictions.Keywords
- Critical paths
- Dual Mode Logic
- Energy efficiency
- Energy-delay optimization
- High performance
