Dual Mode Logic in FD-SOI Technology

Itamar Levi; Alexander Fish

doi:10.1007/978-3-030-40786-5_9

Dual Mode Logic in FD-SOI Technology

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...

Original language	English
Title of host publication	Dual Mode Logic
Place of Publication	Cham, Switzerland
Publisher	Springer
Pages	157-176
Number of pages	20
DOIs	https://doi.org/10.1007/978-3-030-40786-5_9
State	Published - 16 Dec 2020

Keywords

Fully depleted silicon on insulator (FD-SOI)
Ultra-thin body and box (UTBB)
ASIC
CMOS
Multiply-accumulate (MAC)
Buried oxide (BOX)
Drain-induced barrier lowering (DIBL)
Reverse body bias (RBB)
Forward body bias (FBB)
Low-voltage threshold (LVT)
High-voltage threshold (HVT)
Performance
Robustness
DML
Variability
Dynamically adaptable
Carry skip adder (CSA)
Partial product reduction tree (PPRT)
Full adder (FA)
Prediction circuit (PC)
Temperature variation
Near threshold

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10.1007/978-3-030-40786-5_9

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title = "Dual Mode Logic in FD-SOI Technology",

abstract = "Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...",

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KW - Ultra-thin body and box (UTBB)

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KW - Multiply-accumulate (MAC)

KW - Buried oxide (BOX)

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KW - Variability

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KW - Partial product reduction tree (PPRT)

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KW - Prediction circuit (PC)

KW - Temperature variation

KW - Near threshold

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Dual Mode Logic in FD-SOI Technology

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Keywords

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