Dual Mode Logic in FD-SOI Technology

Research output: Chapter in Book/Report/Conference proceedingChapter


Now that we have explored DML operation and efficiency in a conventional bulk CMOS, this chapter evaluates the DML technique in a relatively advanced 28 nm FD-SOI technology. Throughout, we provide fabricated ASIC measurements data to support the analysis and...
Original languageEnglish
Title of host publicationDual Mode Logic
Place of PublicationCham, Switzerland
Number of pages20
StatePublished - 16 Dec 2020


  • Fully depleted silicon on insulator (FD-SOI)
  • Ultra-thin body and box (UTBB)
  • ASIC
  • CMOS
  • Multiply-accumulate (MAC)
  • Buried oxide (BOX)
  • Drain-induced barrier lowering (DIBL)
  • Reverse body bias (RBB)
  • Forward body bias (FBB)
  • Low-voltage threshold (LVT)
  • High-voltage threshold (HVT)
  • Performance
  • Robustness
  • DML
  • Variability
  • Dynamically adaptable
  • Carry skip adder (CSA)
  • Partial product reduction tree (PPRT)
  • Full adder (FA)
  • Prediction circuit (PC)
  • Temperature variation
  • Near threshold


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