Abstract
Address decoders are integral components of random access memories. In higher-performance computing, the timing of address decoders is often critical, especially in applications such as translation lookaside buffer (TLB) and first level data cache. On the other hand, memory power budget and energy consumption are equally critically important for battery-powered devices. Dual Mode Logic (DML) has been shown to combine the support for both requirements in a single circuit. We present a novel DML based address decoder design and compare it with conventional static CMOS and np-CMOS address decoders. Simulations show that DML based address decoder in dynamic mode achieves 31% lower delay compared to conventional static CMOS implementation. In static mode, DML based address decoder reduces the energy consumption by 29% and reaches 10% lower energy-delay product compared to static CMOS address decoder. This is the first time DML is evaluated in 16nm FinFet process.
Original language | English |
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Title of host publication | 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (Electronic) | 9781728133201 |
State | Published - 2020 |
Event | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: 10 Oct 2020 → 21 Oct 2020 |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Volume | 2020-October |
ISSN (Print) | 0271-4310 |
Conference
Conference | 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 |
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City | Virtual, Online |
Period | 10/10/20 → 21/10/20 |
Bibliographical note
Publisher Copyright:© 2020 IEEE
Funding
ACKNOWLEDGMENT Present work was funded by the Israel Innovation Authority in the frame of the GenPro consortium.
Funders | Funder number |
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Israel Innovation Authority |
Keywords
- Dual mode logic (DML)
- Memory address decoder