Dual Mode Logic: A New Paradigm for Digital IC Design

Research output: Book/ReportBookpeer-review

6 Scopus citations

Abstract

This book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic. Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size); Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance; Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells; Illustrates DML efficiency for a variety of VLSI applications.

Original languageEnglish
PublisherSpringer International Publishing
Number of pages185
ISBN (Electronic)9783030407865
ISBN (Print)9783030407858
DOIs
StatePublished - 1 Jan 2020

Bibliographical note

Publisher Copyright:
© Springer Nature Switzerland AG 2021. All rights are reserved.

Keywords

  • CMOS logic
  • Efficient VLSI design
  • Low power integrated circuit design
  • Low voltage IC design
  • design optimization of CMOS logic

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