Double Error Correcting Codes for Memory Macros Under Strict Instantaneous Power Constraints

Certain emerging memory technologies such as Resistive RAM (RRAM) require a relatively large amount of energy when changing the value of a bit. When working under strict instantaneous power constraints, it is necessary to limit the maximum number of bit transitions (bit-flips) that can be made when writing a word. To this end, binary, power-efficient, double-error-correcting (PEDEC) codes are introduced. For standard data widths (multiples of eight bits), PEDEC codes offer reductions in both the number of bit transitions and the memory width. PEDEC codes are encoded systematically, and their redundant part is generated by making use of coset codes that are carefully designed so that their coset leaders are easy to generate. For this reason, PEDEC codes do not require the very large lookup tables required by the competing codes and can be concatenated with any bus encoder.