DML Energy-Delay Tradeoffs and Optimization

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

As shown in the previous chapters, DML design provides very high energy-delay (E-D) optimization flexibility at the gate level. In this chapter, this flexibility is utilized to enhance the energy efficiency and performance of larger combinatorial circuits. In other...
Original languageEnglish
Title of host publicationDual Mode Logic
Place of PublicationCham, Switzerland
PublisherSpringer
Pages75-87
Number of pages13
DOIs
StatePublished - 16 Dec 2020

Keywords

  • Critical path (CP)
  • Carry Look-Ahead (CLA)
  • Adder
  • Energy efficiency
  • High performance
  • Carry Save Adder (CSA)
  • Ripple carry adder (RCA)
  • Carry propagation
  • Input vector
  • DML

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