A distortion analysis based on the large signal behavior of the basic switched-current memory cell is presented. In the first part, based on a closed form solution of the step response, distortion due to the settling error is addressed. In the second part, distortion caused by clock-feedthrough is analyzed. The solutions are compared with simulated and/or measured results. Furthermore, harmonic terms above the fifth are shown to be negligible.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: 31 May 1998 → 3 Jun 1998