Differential Input Output CMOS (DINO-CMOS) –High performance and Energy Efficient Logic Family

A. Fish, M. Haber, I. Levi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Conventional static CMOS logic is the most popular circuit design style in today's digital designs. For many years CMOS logic gates have been preferred mainly for their rail-to-rail swings, strong on/off states, robust operation, large noise margins and low static power. However, one of the main drawbacks of CMOS gates is the need to implement complementary computation networks: the NMOS based pulldown network (PDN) and the pull-up (PUN) PMOS network. Both networks (depending on the logic function of gate) consist of a few stacked transistors. The number of stacked transistors increases with the increase of the Fan-In of the gate, which usually requires upsizing these transistors to improve performance and noise margins. This issue is even more crucial in gates such as NORs, where low mobility stacked PMOS transistors significantly limit the performance of the gate and require large transistors, thus increasing the intrinsic capacitance and power dissipation of the gate. An example of a conventional CMOS NOR3 gate is shown in Fig. 1(a).
Original languageAmerican English
Title of host publication2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
StatePublished - 2017

Bibliographical note

Place of conference:USA


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