Differential input output CMOS (DINO-CMOS)-High performance and energy efficient logic family

M. Haber, I. Levi, Y. Yehoshua, A. Fish

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Conventional static CMOS logic is the most popular circuit design style in today's digital designs. For many years CMOS logic gates have been preferred mainly for their rail-to-rail swings, strong on/off states, robust operation, large noise margins and low static power. However, one of the main drawbacks of CMOS gates is the need to implement complementary computation networks: The NMOS based pulldown network (PDN) and the pull-up (PUN) PMOS network. Both networks (depending on the logic function of gate) consist of a few stacked transistors. The number of stacked transistors increases with the increase of the Fan-In of the gate, which usually requires upsizing these transistors to improve performance and noise margins. This issue is even more crucial in gates such as NORs, where low mobility stacked PMOS transistors significantly limit the performance of the gate and require large transistors, thus increasing the intrinsic capacitance and power dissipation of the gate. An example of a conventional CMOS NOR3 gate is shown in Fig. 1(a).

Original languageEnglish
Title of host publication2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-3
Number of pages3
ISBN (Electronic)9781538637654
DOIs
StatePublished - 2 Jul 2017
Event2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States
Duration: 16 Oct 201718 Oct 2017

Publication series

Name2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume2018-March

Conference

Conference2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/TerritoryUnited States
CityBurlingame
Period16/10/1718/10/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

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