Designing of single precision floating point DSP co-processor

Evgeni R. Overchick, Binyamin Abramov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we show that using FPGA as a CoProcessor with floating point arithmetic can enhance DSP system performance levels through optimized core implementation of critical compute-intensive digital signal processing algorithms such as Fast Fourier Transform (FFT). Our approach is based on building basic building blocks, by implementing optimized, multi-cycle, floating point arithmetic core, which are then used to implement much complex layers of logic such as FFT butterfly, complex multiplier and a DFT block. We present performance results to show that a speedup of 10-19X can be achieved over an optimized FFT DSP Coprocessor implementation on a low cost FPGA such as Cyclone IV.

Original languageEnglish
Title of host publication2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479959877
DOIs
StatePublished - 2014
Externally publishedYes
Event2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014 - Eilat, Israel
Duration: 3 Dec 20145 Dec 2014

Publication series

Name2014 IEEE 28th Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014

Conference

Conference2014 28th IEEE Convention of Electrical and Electronics Engineers in Israel, IEEEI 2014
Country/TerritoryIsrael
CityEilat
Period3/12/145/12/14

Bibliographical note

Publisher Copyright:
© Copyright 2015 IEEE All rights reserved.

Keywords

  • DSP coprocessor
  • FFT
  • FPGA
  • IEEE754
  • Single precision floating point numbers

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