Designing fault tolerant FSM by nano-PLA

S. Baranov, I. Levin, O. Keren, M. Karpovsky

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    20 Scopus citations

    Abstract

    The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides significant reduction of the area without meaningful increasing of a number of crosspoint devices in comparison with known solutions and provides a trade-off between the area and the number of devices in designing FSMs by PLAs.

    Original languageEnglish
    Title of host publication2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
    Pages229-234
    Number of pages6
    DOIs
    StatePublished - 2009
    Event2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009 - Sesimbra-Lisbon, Portugal
    Duration: 24 Jun 200926 Jun 2009

    Publication series

    Name2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009

    Conference

    Conference2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009
    Country/TerritoryPortugal
    CitySesimbra-Lisbon
    Period24/06/0926/06/09

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