Design techniques for HDTV switched-current decimators

Markus Helfenstein, Jose E. Franca, George S. Moschytz

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations


The design of switched-current decimators for wide bandwidth video filtering applications is presented. Applying topologies with only one input commutator to switched-currents allows the design of high speed polyphase input branches with reduced distortion. These concepts were utilized in the implementation of a linear phase 19 tap FIR filter chip with an amplitude response tailored to video applications. It is expected that the prototype filter implemented in a 0.5 μm CMOS process will operate at an input sampling rate of 135MHz and with a decimating factor of 5.

Original languageEnglish
Pages (from-to)195-198
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
Duration: 12 May 199615 May 1996


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