Abstract
The design of switched-current decimators for wide bandwidth video filtering applications is presented. Applying topologies with only one input commutator to switched-currents allows the design of high speed polyphase input branches with reduced distortion. These concepts were utilized in the implementation of a linear phase 19 tap FIR filter chip with an amplitude response tailored to video applications. It is expected that the prototype filter implemented in a 0.5 μm CMOS process will operate at an input sampling rate of 135MHz and with a decimating factor of 5.
| Original language | English |
|---|---|
| Pages (from-to) | 195-198 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 1 |
| State | Published - 1996 |
| Externally published | Yes |
| Event | Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: 12 May 1996 → 15 May 1996 |