Design of a Refresh-Controller for GC-eDRAM Based FIFOs

Tzachi Noy; Adam Teman

doi:10.1109/TCSI.2020.2998582

Design of a Refresh-Controller for GC-eDRAM Based FIFOs

Tzachi Noy, Adam Teman

Bar-Ilan University - The Alexander Kofkin Faculty of Engineering

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a 2× reduction in both area and power as compared to SRAM.

Original language	English
Article number	9108393
Pages (from-to)	4804-4817
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	67
Issue number	12
DOIs	https://doi.org/10.1109/TCSI.2020.2998582
State	Published - Dec 2020

Bibliographical note

Funding Information:
Manuscript received December 24, 2019; revised March 31, 2020; accepted May 25, 2020. Date of publication June 4, 2020; date of current version December 1, 2020. This work was supported in part by the Kamin Program of the Israel Innovation Authority under Project 61907, and in part by the Israel Science Foundation under Grant 996/18. This article was recommended by Associate Editor I. Kale. (Corresponding author: Tzachi Noy.) The authors are with the Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel (e-mail: tzachi.noy@biu.ac.il; adam.teman@biu.ac.il).

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

First-in first-out (FIFO)
embedded dynamic random access memory (eDRAM)
gain-cells (GCs)
low power
memory availability
retention time

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10.1109/TCSI.2020.2998582

Cite this

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abstract = "First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a 2× reduction in both area and power as compared to SRAM.",

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Design of a Refresh-Controller for GC-eDRAM Based FIFOs

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Keywords

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