Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Pascal Andreas Meinerzhagen; Onur Andiç; Jürg Treichler; Andreas Peter Burg

doi:10.1145/1973009.1973078

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.

Original language	English
Title of host publication	GLSVLSI'11 - Proceedings of the 2011 Great Lakes Symposium on VLSI
Pages	343-346
Number of pages	4
DOIs	https://doi.org/10.1145/1973009.1973078
State	Published - 2011
Externally published	Yes
Event	21st Great Lakes Symposium on VLSI, GLSVLSI 2011 - Lausanne, Switzerland Duration: 2 May 2011 → 4 May 2011

Publication series

Name	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference	21st Great Lakes Symposium on VLSI, GLSVLSI 2011
Country/Territory	Switzerland
City	Lausanne
Period	2/05/11 → 4/05/11

Keywords

Embedded memory
Gain cell
High density
Multilevel storage
Process variations
Read failure

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10.1145/1973009.1973078

Cite this

Meinerzhagen, P. A., Andiç, O., Treichler, J., & Burg, A. P. (2011). Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. In GLSVLSI'11 - Proceedings of the 2011 Great Lakes Symposium on VLSI (pp. 343-346). (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI). https://doi.org/10.1145/1973009.1973078

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title = "Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems",

abstract = "This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations.",

keywords = "Embedded memory, Gain cell, High density, Multilevel storage, Process variations, Read failure",

author = "Meinerzhagen, {Pascal Andreas} and Onur Andi{\c c} and J{\"u}rg Treichler and Burg, {Andreas Peter}",

year = "2011",

doi = "10.1145/1973009.1973078",

language = "אנגלית",

isbn = "9781450306676",

series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

pages = "343--346",

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note = "21st Great Lakes Symposium on VLSI, GLSVLSI 2011 ; Conference date: 02-05-2011 Through 04-05-2011",

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Meinerzhagen, PA, Andiç, O, Treichler, J & Burg, AP 2011, Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. in GLSVLSI'11 - Proceedings of the 2011 Great Lakes Symposium on VLSI. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 343-346, 21st Great Lakes Symposium on VLSI, GLSVLSI 2011, Lausanne, Switzerland, 2/05/11. https://doi.org/10.1145/1973009.1973078

Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. / Meinerzhagen, Pascal Andreas; Andiç, Onur; Treichler, Jürg et al.
GLSVLSI'11 - Proceedings of the 2011 Great Lakes Symposium on VLSI. 2011. p. 343-346 (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems

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