Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs across the Design and Variations Space

Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic refresh cycles, which are determined according to the worst-case data retention time (DRT) across process, voltage and temperature (PVT) variations. Even though several DRT characterization methodologies have been reported in literature, they often require unfeasible run-times for accurate DRT evaluation, or they result in highly pessimistic design margins due to their inaccuracy. In this work, we propose an current-based DRT (IDRT) characterization methodology that enables accurate DRT evaluation across process variations without the need for a large number of costly electronic design automation (EDA) software licenses. The presented approach is compared with other DRT characterization methodologies for both accuracy and run-time across several gain-cell structures at different process technologies, providing less than a 4% DRT error and over 100× shorter run-time compared to a conventional DRT evaluation methodology.

Original languageEnglish
Article number9003520
Pages (from-to)1207-1217
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume67
Issue number4
DOIs
StatePublished - Apr 2020

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • Embedded dynamic random access memory (eDRAM)
  • embedded memory
  • gain-cells (GCs)
  • retention time

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